(1) Field of the Invention
This invention relates to a solid-state imaging device which has a plurality of photoelectric elements packed in a semiconductor surface region. More particularly, it relates to a solid-state imaging device which has photoelectric elements for reading out from photodiodes photo information stored therein.
(2) Description of the Prior Art
FIG. 1A shows a prior-art solid-state imaging device. In this figure, numeral 11 designates a gate line, numeral 12 an output line, numeral 13 a switching metal-oxide-semiconductor (MOS) transistor, and numeral 14 a photo PN-junction diode. The sectional structure of the solid-state imaging device corresponding to one picture element is illustrated in FIG. 1B. In this figure, numeral 15 indicates a silicon dioxide (SiO.sub.2) film, and numeral 16 a p-conductivity type silicon substrate. The gate electrode 11 is made of, for example, polycrystalline silicon. An n.sup.+ -conductivity type diffused layer forms the signal output line 12. Another diffusion layer of the n.sup.+ -conductivity type forms the photosensitive region of the photodiode 14. Shown at 17 is a depletion layer which spreads in the substrate 16.
In this system, photo-information is stored in the junction capacitance between the p-type substrate 16 and the n.sup.+ -type diffused layer 14. As discussed below, the storage capacitance is roughly one order smaller than in a surface MOS diode to be described later. Letting V.sub.H denote the pulse amplitude of an operating voltage, V.sub.T the threshold voltage of the MOS transistor switch, .epsilon..sub.S the dielectric constant of silicon, q the electronic charge, V.sub.bi the built-in potential, N.sub.A the impurity concentration of the substrate, and N.sub.D the impurity concentration of the n.sup.+-type diffused layer, the thickness X.sub.D of the depletion layer 17 is represented by the following equation: ##EQU1## By way of example, let it be supposed that V.sub.H (.about.5 V)-V.sub.T (.about.0.7 V) +V.sub.bi (.about.0.6 V)=5 V, N.sub.A =1.times.10.sup.15 cm.sup.-3 and N.sub.D =1.times.10.sup.19 cm.sup.-3. Then, the thickness of the depletion layer becomes: EQU X.sub.D .perspectiveto.2.1 .mu.m (2)
The capacitance C.sub.D per unit area becomes: EQU C.sub.D =.epsilon..sub.S /X.sub.D .apprxeq.0.5.times.10.sup.-8 F/cm.sup.2 (3)
On the other hand, in another prior art device shown in FIGS. 2A and 2B wherein the MOS structure (surface MOS diode) is employed for the capacitance, when the thickness T.sub.OX of a silicon dioxide film 15 under an electrode 19 is assumed to be 1,000 A and .epsilon..sub.OX denotes the dielectric constant of silicon dioxide, the capacitance C.sub.OX per unit area becomes: EQU C.sub.OX =.epsilon..sub.OX /T.sub.OX .apprxeq.3.5.times.10.sup.-8 F/cm.sup.2 (4)
In the case of FIGS. 1A and 1B, the capacitance per unit area is as small as 1/7 of that in the case of FIGS. 2A and 2B, and hence, the packing density is not enhanced.
The prior art device in FIGS. 2A and 2B consists in an expedient wherein an inversion layer in a substrate surface based on the MOS structure is utilized instead of that based on the PN-junction diode 14 in FIGS. 1A and 1B. In this case, a high electric field exists in the Si surface, so that most of hole-electron pairs generated in Si contribute to optical information. Since, however, the greater part of light illuminating the device is absorbed by the electrode 19, the total photosensitivity and the sensitivity in the blue region are conspicuously lower than those of the prior-art device in FIGS. 1A and 1B. In order to enhance the photosensitivity, the thickness of the electrode 19 may be lessened. With the present technology, however, it is very difficult to make the thickness of the electrode 19 less than 0.3 .mu.m without raising the resistance.